In recent years, a system-in-package has been focused for semiconductor packaging technology. According to such a technology, plural semiconductor chips, each having an integrated circuit, are mounted at a high density to fabricate a high performance system for a short period of time. Especially, a system-in-package is required to be applied to a layered type of semiconductor package, in which plural semiconductor chips are layered in a three dimensional manner to minimize a size of the package. In response to such a demand, for example, Japanese patent publication No. 2005-236245A describes a semiconductor package, in which semiconductor chips, having through electrodes, are layered on a mounting chip, called “semiconductor interposer”.
[Patent Related Publication] No. 2005-236245A
For fabricating a semiconductor package, according to a conventional method, a semiconductor interposer, which has been shaped to be thinner and diced into individual chips, is prepared; and a plurality of semiconductor chips is layered on it.
However, according to the above described conventional method, a thin and small piece of semiconductor interposer is hardly handled during packaging process, and therefore, it is difficult to improve work efficiency. As a result, semiconductor chips may easily have some damages and a yield rate may be lowered. Handling ability of a semiconductor interposer during packaging process could be improved by shaping the semiconductor interposer to have a larger thickness. However, a semiconductor package would have a larger thickness undesirably and it would become difficult to form through electrodes in the semiconductor interposer and difficult to fill material in the through holes.